The present invention relates to a semiconductor device, and more particularly, to a functional macro chip for a chip-on-chip configuration.
A semiconductor device having a chip-on-chip configuration includes a first chip and a plurality of second chips, or functional macro chips, bonded to the surface of the first chip. The functional macro chips are packaged together with the first chip. To reduce costs, such a semiconductor device requires miniaturization of the functional macro chips.
FIG. 1 is a schematic side view showing a semiconductor device 100 having a chip-on-chip configuration. A first chip 1 has a surface on which bumps B are formed. A plurality of functional macro chips 2 are bonded to the first chip 1 by means of the bumps B. Pads (not shown) are formed along the periphery of the first chip 1 and connected to external pins (not shown) by bonding wires 3.
FIG. 2 is a schematic plan view showing a prior art layout of a functional macro chip 2 shown in FIG. 1. The functional macro chip 2 includes a macro region 4 and a pad region 5, which is formed surrounding the macro region 4. The pad region 5 includes test pads and I/O cells used during wafer testing (operational testing of each functional macro chip 2). The pad region 5 becomes unnecessary after the wafer testing.
FIG. 3 is a schematic plan view showing another prior art layout of the functional macro chips 2 shown in FIG. 1 and formed on a wafer W. A pad region 5 is formed surrounding the macro region 4 of each functional macro chip 2. The macro regions 4 that are adjacent to each other share the pad region 5. This reduces the area occupied by the pad regions 5 on the wafer W and increases the quantity of functional macro chips 2 that may be formed from a single wafer W.
After wafer testing, the functional macro chips 2 are cut apart from one another along scribe lines 6, which are shown in FIG. 3.
Japanese Laid-Open Patent Publication No. 2001-94037 describes a semiconductor device including a first chip and a second chip mounted on the first chip. Bumps, which are formed on the first chip, are provided with test signals from a test probe to check the operation of the second chip.